Digital Electronics: What is a Flip-Flop?
In the parlance of electronics, a flip-flop is a special type of gated latch. The difference between a flip-flop and a gated latch is that in a flip-flop, the inputs aren’t enabled merely by the presence of a HIGH signal on the CLOCK input.
Instead, the inputs are enabled by the transition of the CLOCK input. Thus, at the moment that the clock input transitions from low to high, the inputs are briefly enabled. Once the clock stabilizes at the HIGH setting, the output state of the flip-flop is latched until the next clock pulse.
Flip-flops are often said to be edge-triggered because it’s the edge of the clock signal that triggers the flip-flop. When used in clock-driven computer circuits, edge-triggering is an important characteristic because it helps circuit designers maintain better control over the timing in circuits that contain hundreds or perhaps thousands of flip-flops.
The circuitry that enables a flip-flop to respond to just the leading edge can be pretty complicated. One of the simplest methods is to feed the clock input into a NAND gate, passing one of the legs through an inverter. This works because in all logic gates, there is a very small delay between the time a signal arrives at the input and the correct signal arrives at the output.
Initially, the clock input is LOW. The inverter causes the first input to the NAND gate (marked 1) to be HIGH, while the second input is LOW. Because the inputs aren’t both HIGH, the output from the NAND gate at point 2 is HIGH. The second inverter inverts the NAND gate output so the final output from the circuit at point 3 is LOW, just like the clock input.
When the clock input goes high, the second input to the NAND gate goes high immediately. However, it takes a few milliseconds for the inverter to respond, so for those few milliseconds, the output from the inverter is still HIGH.
Thus, both inputs to the NAND gate are HIGH for a few milliseconds, which causes the output from the NAND gate at point 2 to go LOW. Then, the second NOT gate inverts the NAND gate output, causing the output at point 3 in the signal to go HIGH for a brief moment.
Once the first NOT gate catches up and its output goes LOW (at point 1), the NAND gate responds to the LOW and HIGH input by setting its output to HIGH at point 2. The second NOT gate then inverts that output at point 3.
The net result of the circuit is that long clock pulses are turned into short clock pulses. The duration between the pulses remains the same, but the HIGH part of the pulse becomes much shorter.
Flip-flops are designed for use in circuits that use steady clock pulses. An easy way to provide clock pulses for a flip-flop circuit is to use a 555 timer IC. However, the input source for the CLOCK input of a flip-flop doesn’t have to be an actual clock; it can also be a one-shot input triggered by a pushbutton.